Howard’s Blog

I ran into a jam where I needed some USB cables with right-angled connectors on the “B” end of the cable. I had looked for these several years ago with no luck. This time, a coleague pointed me to usbfirewire.com and they had cables that do the trick. I just received them today via Priority Mail, and they look and work great.

-Howard

I needed to buy another Lattice ISP Download parallel port cable for programming CPLDs. While browsing the Lattice on-line store , I found that their Mach XO Starter kit was $99.00 and included the cable. The cable alone goes for $65.00. So I ordered the kit from their site. When it arrived, I was happy to find that the parallel port cable has changed for the better. It is now a one-piece moulded cable, and the device-end termination gives you the choice of fly-wire, standard 1×8-pin or 2×5-pin JTAG interface. You can pick the correct pinout for your application by using either the fly wires direcly to your board, or using either the supplied 1×8 or 2×5 adapters. The datasheet for this cable is available here for download.

I tried this cable with an existing board design that I had that uses the Mach M4A5 device, and it worked great.

After trying to write a 720K 3.5″ Disk (DS/DD) in a Memorex (Teac) USB Floppy drive with NtRawrite.exe and not being able to read it back using a regular motherboard-connected 3.5″ floppy drive, I decided to take a look into this. Since it was an urgent requirement for me to be able to do this, I went to Fry’s Electronics, and bought one of each brand of USB floppy drive, except the Targus, which looked to be the same as the Teac. In all, including the Teac and the internal motherboard connected floppy drive, I had five drives:

1. Motherboard 3.5″ Floppy Drive
2. IOMega “Floppy Plus” CRE-01A (CITIZEN X1-USB Floppy)
3. Memorex (Teac) FD-05PUB (TEAC FD-05PUB USB Device)
4. Q-Stor QFDTU14W (W was covered up by a sticker) (NEC USB UF000x USB Device)
5. Sony MPF88E (SONY USB-FDU USB Device)

After trying each of the USB floppy drives with 720K and 1.44M disks, I found that the Teac was the only one that did not work with the disks from the others. I was able to format/write/read the Teac, but when I tried to use the disk in another drive, Windows XP told me that the disk was not formatted.

Then I considered that maybe the Teac drive was defective, rather than incompatible. After going to Fry’s and exchanging the Teac for another drive, I repeated the tests with this drive, and it proved to be compatible after all.

I did find out some interesting things about USB floppy drives in general:

1. They are not simply a USB function controller connected to a plain old 34-pin floppy drive interface. Instead, the floppy drive itself contains an integrated USB controller.
2. All of the drives except the IOMega installed under Windows XP without any user intervention.
The IOMega required me to install the drivers supplied in the package. After doing that, the
drive worked flawlessly. The only drawback to this is that if you take the IOMega drive to a new machine, you’d have to bring the driver CD-ROM with you, or download the drivers from IOMega. I tried downloading the driver from IOMega’s site, and it is very easy, but requires you to create an account on their web site.
3. The IOMega “Floppy Plus” is actually a Citizen USB floppy drive connected to another board which contains a USB 1.1 Hub Controller chip and a 7-in-1 Flash Media Card controller chip. As far as Windows is concerned, the IOMega drive is three devices: a USB 1.1 hub, a 7-in-1 media card reader, and a Citizen USB Floppy drive connected to it. The Media card reader comes up as two drives. One drive for CF, and another for SM/MS/SD/MMC cards, and of course the floppy also comes up as a separate drive.

After testing these drives, I verified that I was able to write a 720K disk image with NtRawWrite on each of the drives, and verify them using the motherboard-connected floppy drive. So, in the end, aside from the original Teac drive being defective, it appears that these USB floppy drives are compatible.

My web hosting provider raised their disk space limit to 40GB, so I will be re-posting the files that I previously took off-line. 40GB should provide enough room for this site for the forseeable future.

-Howard

WANTED:

I am particularly looking for the following manuals to post in the S-100 Manuals Archive:

Thanks,
Howard

The IEEE-696/S-100 Bus is known for its interoperability problems. Many times, boards from different manufacturers don’t work well together in a system. I’ve decided to investigate this problem, and determine a root cause. In the first part of my investigation, I look at the IEEE-696 strobe signals. The strobe signals tell slave devices “when” to do something, whereas the status signals (sMEMR, sWO, sINP, sOUT, sHLTA, sHLDA, along with the address bus, which I consider to be part of the status signals for purposes of this discussion) tell the slave what do do. When determining “what” to do (ie, assert a chip select (CS#) on a particular device) the status information should be used. When taking an action, such as reading data out of a device using the RD#, or writing data to it (WR#), the strobes should be used.

I’ve looked at the timing waveforms for all the 8080, 8085, and Z80 IEEE-696 / S-100 CPU cards that I have, and found about three general variations:

1. Cards whose strobes come out early.
2. Cards whose strobes adhere to the IEEE-696 Spec. (very few)
3. Cards whose strobes come out late.

The relevant strobes on the IEEE-696/S-100 bus are:

pSYNC / pSTVAL (status valid)
pDBIN (read strobe)
pWR# (write strobe)

I’ve found that in all cases, I was able to generate a mostly valid status strobe from pSYNC. Since various S-100 CPU cards have different ideas of what pSTVAL is supposed to be (some use the Phi-1 clock, some generate the IEEE-696 style pSYNC, and some don’t generate any signal at all.)

The mostly valid status strobe comes from gating pSYNC with the low state of the S-100 Phi clock (which is the buffered CPU Phi-2 clock.) In most CPU cards, this generates a nice, single strobe. In some cases however, this generates two strobe pulses, because the Phi-2 clock being low happens in the middle of the pSYNC cycle, and lasts for less than the full pSYNC assertion. This should not cause any problems for slave card operation, because the slave card should latch the S-100 address and status lines with this strobe, and so if the strobe happens twice, as long as the status/address lines don’t change (which they shouldn’t) everything will be ok.

The cards I looked at were:

California Computer Systems CCS-2810 (2- and 4-MHz operation)
California Computer Systems CCS-2820 (4-MHz operation)
CompuPro 8085/8088 (2- and 5-MHz operation)
Cromemco ZPU (2- and 4-MHz operation)
Cromemco DPU (4-MHz operation)
North Star ZPB-A2 (4-MHz operation)
IMS Z80 (4-MHz Operation)
IMSAI MPU-A (2-MHz 8080A)
Ithaca Audio 1010 Rev 2.0 (4-MHz operation)
Ithaca Audio IA-2000 (4-MHz operation)
Vector Graphics ZCB (4-MHz operation)

Manuals for most of these boards can be found at here.

I’d appreciate feedback on which S-100 CPU cards people are using in their systems, and with what other combinations of boards.

Next time, I will talk about the read and write strobes pDBIN and pWR#.

-Howard